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vishay siliconix si5424dc document number: 73776 s-83054-rev. b, 29-dec-08 www.vishay.com 1 n-channel 30-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 available ? trenchfet ? power mosfet applications ? load switch - notebook pc product summary v ds (v) r ds(on) ( ) i d (a) a q g (typ.) 30 0.024 at v gs = 10 v 6 11 nc 0.030 at v gs = 4.5 v 6 orderin g information: si5424dc-t1-e3 (lead (p b )-free) SI5424DC-T1-GE3 (lead (p b )-free and halogen-free) chipfet 1206-8 d d d g d d d s 1 bottom v ie w marking code af xxx lot tracea b ility and date code part # code n -channel mosfet g d s notes: a. package limited. b. surface mounted on 1? x 1? fr4 board. c. t = 5 s. d. see solder profile (www.vishay.com/doc?73257 ) . the chipfet 1206-8 is a leadless package. t he end of the lead terminal is exposed copper (not plated) as a result of the singulatio n process in manufacturing. a solder fill et at the exposed copper tip cannot be guara nteed and is not required to ensure adequate botto m side solder interconnection. e. rework conditions: manual soldering with a sol dering iron is not recommended for leadless components. f. maximum under steady state conditions is 80 c/w. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 25 continuous drain current (t j = 150 c) t c = 25 c i d 6 a a t c = 70 c 6 a t a = 25 c 6 a t a = 70 c 6 a pulsed drain current i dm 40 continuous source-drain diode current t c = 25 c i s 5.2 a t a = 25 c 2.1 b, c single pulse avalanche current l = 0.1 mh i as 16 avalanche energy e as 12.8 mj maximum power dissipation a t c = 25 c p d 6.25 w t c = 70 c 4 t a = 25 c 2.5 b, c t a = 70 c 1.6 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) d, e 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, f t 5 s r thja 40 50 c/w maximum junction-to-foot (drain) steady state r thjf 15 20
www.vishay.com 2 document number: 73776 s-83054-rev. b, 29-dec-08 vishay siliconix si5424dc notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 v v ds temperature coefficient v ds /t j i d = 250 a 19.4 mv/c v gs(th) temperature coefficient v gs(th) /t j - 4.6 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.1 2.3 v gate-source leakage i gss v ds = 0 v, v gs = 25 v 100 ns zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 40 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 4.8 a 0.020 0.024 v gs = 4.5 v, i d = 4.22 a 0.024 0.030 forward transconductance a g fs v ds = 15 v, i d = 4.8 a 17 s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz 950 pf output capacitance c oss 230 reverse transfer capacitance c rss 180 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 4.8 a 21 32 nc v ds = 15 v, v gs = 4.5 v, i d = 4.8 a 11 17 gate-source charge q gs 3.2 gate-drain charge q gd 4.2 gate resistance r g f = 1 mhz 2.2 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 2.63 i d ? 5.7 a, v gen = 4.5 v, r g = 1 17 26 ns rise time t r 75 113 turn-off delay time t d(off) 22 33 fall time t f 12 18 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 2.5 i d ? 6 a, v gen = 10 v, r g = 1 10 15 rise time t r 38 57 turn-off delay time t d(off) 26 40 fall time t f 914 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 6 a pulse diode forward current i sm 40 body diode voltage v sd i s = 4.3 a, v gs = 0 v 0.8 1.2 v body diode reverse recovery time t rr i f = 4.3 a, di/dt = 100 a/s, t j = 25 c 24 36 ns body diode reverse recovery charge q rr 11 17 nc reverse recovery fall time t a 9 ns reverse recovery rise time t b 15
document number: 73776 s-83054-rev. b, 29-dec-08 www.vishay.com 3 vishay siliconix si5424dc typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge 0 10 20 30 40 0.0 0.6 1.2 1. 8 2.4 3.0 v gs = 3 v v gs = 2 v v gs = 4 v v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d v gs = 10 thr u 5 v 0.01 0.02 0.03 0.04 0 8 16 24 32 40 v gs = 10 v v gs = 4.5 v - on-resistance (m ) r ds(on) i d - drain c u rrent (a) 0 2 4 6 8 10 0 6 12 1 8 24 v ds = 15 v v ds = 24 v i d = 6 a - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 1 2 3 4 5 0.0 0.6 1.2 1. 8 2.4 3.0 t j = 25 c t j = 125 c t j = - 55 c v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d c oss c rss 0 300 600 900 1200 1500 0 5 10 15 20 25 30 c iss v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v , i d = 4. 8 a v gs = 4.5 v , i d = 4.2 a t j -j u nction temperat u re (c) ( n ormalized) - on-resistance r ds(on)
www.vishay.com 4 document number: 73776 s-83054-rev. b, 29-dec-08 vishay siliconix si5424dc typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 0.001 0.1 0.01 1 10 20 t a = 150 c t a = 25 c v sd -so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 2.0 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0246 8 10 i d = 4. 8 a t a = 25 c t a = 125 c - on-resistance ( ) r ds(on) v gs - gate-to-so u rce v oltage ( v ) 0 30 50 10 20 po w er ( w ) time (s) 40 1 100 600 10 10 -1 10 -2 10 -3 safe operating area, junction-to-ambient 10 ms 100 ms dc 1 s 10 s 1 ms 0.001 100 1 0 0 1 1 1 . 0 0.01 10 0.1 10 t a = 25 c single p u lse b v dss limited limited b y r ds(on) * v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified - drain c u rrent (a) i d
document number: 73776 s-83054-rev. b, 29-dec-08 www.vishay.com 5 vishay siliconix si5424dc typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 4 8 12 16 0 25 50 75 100 125 150 package limited t c - case temperat u re (c) i d - drain c u rrent (a) power derating 0 2 4 6 8 0 25 50 75 100 125 150 po w er dissipation ( w ) t c - case temperat u re (c)
www.vishay.com 6 document number: 73776 s-83054-rev. b, 29-dec-08 vishay siliconix si5424dc typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73776 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 8 0 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance
package information vishay siliconix document number: 71151 15-jan-04 www.vishay.com 1 1206-8 chipfet c e e 1 e d a 65 7 8 34 2 1 4 l 5678 4321 4 s b 2x 0.10/0.13 r backside view x notes: 1. all dimensions are in millimeaters. 2. mold gate burrs shall not exceed 0.13 mm per side. 3. leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. dimensions exclusive of mold gate burrs. 5. no mold flash allowed on the top and bottom lead surface. detail x c1 millimeters inches dim min nom max min nom max a 1.00 ? 1.10 0.039 ? 0.043 b 0.25 0.30 0.35 0.010 0.012 0.014 c 0.1 0.15 0.20 0.004 0.006 0.008 c1 0 ? 0.038 0 ? 0.0015 d 2.95 3.05 3.10 0.116 0.120 0.122 e 1.825 1.90 1.975 0.072 0.075 0.078 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.65 bsc 0.0256 bsc l 0.28 ? 0.42 0.011 ? 0.017 s 0.55 bsc 0.022 bsc 5 nom 5 nom ecn: c-03528?rev. f, 19-jan-04 dwg: 5547
an811 vishay siliconix document number: 71126 12-dec-03 www.vishay.com 1 single-channel 1206-8 chipfet power mosfet recommended pad pattern and thermal performance introduction new vishay siliconix chipfets in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. the 1206-8 chipfet has the same footprint as the body of the little foot tsop-6, and can be thought of as a leadless tsop-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger so-8. this technical note discusses the single-channel chipfet 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. pin-out figure 1 shows the pin-out description and pin 1 identification for the single-channel 1206-8 chipfet device. the pin-out is similar to the tsop-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. the legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. single 1206-8 chipfe t d d d g d d d s 1 bottom view figure 1. for package dimensions see the 1206-8 chipfet package outline drawing ( http://www.vishay.com/doc?71151 ). basic pad patterns the basic pad layout with dimensions is shown in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ). this is sufficient for low power dissipation mosfet applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. figure 2. footprint with copper spreading 80 mil 68 mil 28 mil 26 mil the pad pattern with copper spreading shown in figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. the drain copper area is 0.0054 sq. in. or 3.51 sq. mm). this will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. the addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. an example of this method is implemented on the vishay siliconix evaluation board described in the next section (figure 3). the vishay siliconix evaluation board for the single 1206-8 the chipfet 1206-08 evaluation board measures 0.6 in by 0.5 in. its copper pad pattern consists of an increased pad area around the six drain leads on the top-side?approximately 0.0482 sq. in. 31.1 sq. mm?and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. the outer package outline is for the 8-pin dip, which will allow test sockets to be used to assist in testing. the thermal performance of the 1206-8 on this board has been measured with the results following on the next page. the testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square fr4 pcb with copper on both sides of the board.
an811 vishay siliconix www.vishay.com 2 document number: 71126 12-dec-03 front of board figure 3. back of board vishay.com chipfet thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the 1206-8 chipfet measured as junction-to-foot thermal resistance is 15 c/w typical, 20 c/w maximum for the single device. the ?foot? is the drain lead of the device as it connects with the body. this is identical to the so-8 package r jf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the single-channel 1206-8 chipfet is 80 c/w steady state, compared with 68 c/w for the so-8. maximum ratings are 95 c/w for the 1206-8 versus 80 c/w for the so-8. testing to aid comparison further, figure 4 illustrates chipfet 1206-8 thermal performance on two different board sizes and three different pad patterns. the results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. the measured steady state values of r ja for the single 1206-8 chipfet are : 1) minimum recommended pad pattern (see figure 2) on the evaluation board size of 0.5 in x 0.6 in. 156 c/w 2) the evaluation board with the pad pattern described on figure 3. 111 c/w 3) industry standard 1? square pcb with maximum copper both sides. 78 c/w the results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. in this example, a 45 c/w reduction was achieved without having to increase the size of the board. if increasing board size is an option, a further 33 c/w reduction was obtained by maximizing the copper from the drain on the larger 1? square pcb. time (secs) figure 4. single 1206 ? 8 chipfet thermal resistance (c/w) 0 1 160 40 80 100 1000 120 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square pcb single evb min. footprint summary the thermal results for the single-channel 1206-8 chipfet package display similar power dissipation performance to the so-8 with a footprint reduction of 80%. careful design of the package has allowed for this performance to be achieved. the short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the tsop-6 body size. associated document 1206-8 chipfet dual thermal performance, an812 (http://www.vishay.com/doc?71127) .
application note 826 vishay siliconix www.vishay.com document number: 72593 2 revision: 21-jan-08 application note recommended minimum pads for 1206-8 chipfet ? 0.080 (2.032) recommended mi nimum pads dimensions in inches/(mm) 0.093 (2.357) 0.036 (0.914) 0.022 (0.559) 0.026 (0.650) 0.016 (0.406) 0.010 (0.244) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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